DocumentCode :
652947
Title :
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects
Author :
Morris, Randy ; Kodi, Avinash ; Louri, Ahmed
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Athens, OH, USA
fYear :
2013
fDate :
2-2 June 2013
Firstpage :
1
Lastpage :
1
Abstract :
As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and nanophotonics that can deliver high on-chip bandwidth and low energy/bit to achieve a high-throughput, reconfigurable and scalable NoC for many-core systems. Our simulation results indicate that the execution time can be reduced up to 25% and energy consumption reduced by 23% for Splash-2, PARSEC, SPEC CPU2006 and synthetic benchmarks for 64-core and 256-core versions.
Keywords :
integrated circuit interconnections; integrated circuit reliability; nanophotonics; network-on-chip; 256-core versions; 3D stacked reconfigurable nanophotonic interconnects; 64-core versions; NoC; PARSEC; SPEC CPU2006; Splash-2; energy-efficiency; many-core systems; metallic interconnects; network-on-chips; performance evaluation; scalability evaluation; synthetic benchmarks; technology solutions; Bandwidth; Educational institutions; Integrated optics; Optical fibers; Optical ring resonators; Three-dimensional displays; Nanophotonics; NoCs; Reconfiguration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Level Interconnect Prediction (SLIP), 2013 ACM/IEEE International Workshop on
Conference_Location :
Austin, TX
Type :
conf
DOI :
10.1109/SLIP.2013.6681676
Filename :
6681676
Link To Document :
بازگشت