IBM CMOS compatible photonics and traveling wave electro-optic modulator design

Author

Gill, Douglas

fYear

2013

fDate

2-2 June 2013

Firstpage

1

Lastpage

1

Abstract

Summary form only given. This talk will give a general overview of the IBM Silicon Photonics program and specifically discuss CMOS compatible traveling wave electro-optic modulator design. A Non-Return-to-Zero Transmitter-link penalty calculation protocol for Mach-Zehnder Interferometric modulators based on the phase shifter efficiency-loss figure-of-merit will be presented. Our Transmitter-link penalty analysis protocol allows one to easily assess an expected penalty estimation from only the RF Vpp drive, modulator efficiency loss FOM, and the assumption that transmitter bandwidth is sufficient to support the link data rate, which allows system designers to better understand how device-level performance metrics impact system link budget.

Keywords

CMOS analogue integrated circuits; electro-optical devices; modulators; phase shifters; CMOS compatible traveling wave electro-optic modulator design; IBM CMOS compatible photonics; IBM silicon photonics program; Mach-Zehnder interferometric modulators; RF voltage drive; device-level performance metrics; expected penalty estimation; link data rate; modulator efficiency loss FOM; nonreturn-to-zero transmitter-link penalty calculation protocol; phase shifter efficiency-loss figure-of-merit; system link budget; transmitter bandwidth; transmitter-link penalty analysis protocol; CMOS integrated circuits; Electrooptic modulators; Phase shifting interferometry; Photonics; Protocols; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

System Level Interconnect Prediction (SLIP), 2013 ACM/IEEE International Workshop on

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/SLIP.2013.6681677

Filename

6681677