Toward quantifying the IC design value of interconnect technology improvements

As technology scales, wire delay due to interconnect resistance (R) and capacitance (C) is increasing. Thus, improvement of middle-of-line and back-end-of-line (BEOL) materials and process technology (e.g., to achieve reduced barrier material thickness or dielectric permittivity) has always been a key goal in the technology roadmap. However, to date there has not been any systematic quantification of the value of BEOL technology improvements on integrated circuit (LC) design metrics. In this work, we create a framework to study the impact of improvements in interconnect technology on IC designs. Using 45nm technology and benchmark designs from public sources, we map reductions of interconnect resistance and/or capacitance to resulting impacts on design power, performance and area - for various types of physical design and operating contexts. By quantifying potential benefits of interconnect technology improvements at a block or core level, our proposed framework complements lower-level (e.g., critical-path) projections. We believe that this type of early assessment can be useful to guide BEOL technology investments and targets, especially as technology improvements require ever-increasing resources and focus in R&D efforts.