Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors

Since the end of the Megahertz Race, the main factor in improving processor performance has been the increase of the number of cores integrated on a single chip. While four-, six- and eight-core processors are standard today, future designs with even higher core counts encounter scalability problems concerning the on-chip interconnect and power dissipation. For the interconnect problem, regular tile-based designs that employ a Network-on-Chip to provide inter-core connectivity have been proposed as solution. To mitigate the power consumption issue, we present a system for exploiting idle time in high-performance applications by reducing a core´s frequency, thus saving power without affecting performance. The system relies on annotation of synchronizing communication calls and has been shown to reduce the energy requirements of considered applications by 20-30%, while introducing negligible overhead in terms of runtime.