Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration

Author

Li Shiwen ; Dang Hua ; Gao Peng ; Gui Xiaoyan ; Chen Zhiming ; Wang Xinghua ; Zhong Shunan

Author_Institution

Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China

fYear

2013

fDate

20-23 Aug. 2013

Firstpage

1829

Lastpage

1833

Abstract

A 1Gsps 5-bit Flash ADC is designed with offset calibration and fabricated in TSMC 0.18 μm CMOS process. This design contains the basic Flash ADC circuit and offset calibration. To achieve a high speed sampling rate, preamplifier with latch is applied. And in order to reduce the offset which is caused by mismatch, a type of calibration with current trimming is analysed and realized. The results of chip test with calibration show that the SNDR reaches 29.6dB and the SFDR reaches 45.6dB under the input frequency of 39MHz with 1GHz sampling rate.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; flip-flops; preamplifiers; CMOS flash ADC; analog-digital converter; high speed sampling; latch circuit; offset calibration; preamplifier circuit; CMOS integrated circuits; Calibration; Clocks; Computer architecture; Latches; Preamplifiers; Registers; Flash ADC; offset calibration; preamplifier with latch;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing and Communications (GreenCom), 2013 IEEE and Internet of Things (iThings/CPSCom), IEEE International Conference on and IEEE Cyber, Physical and Social Computing

Conference_Location

Beijing

Type

conf

DOI

10.1109/GreenCom-iThings-CPSCom.2013.339

Filename

6682350