An Effective Capacitance Model for 28-nm and Beyond Copper Interconnect

In 28-nm CMOS technology, copper interconnect becomes complicated as the dielectric copper diffusion barrier and low-κ damage compromise capacitance gain from low-κ implementation. As a consequence, accurate and effective estimation of the interconnect capacitance is a very challenging task during integration and unit process development. This paper attempts to integrate the impacts of the technological innovations and presents a new compact capacitance model by modifying one of the existing empirical models. The new model demonstrates good agreement with Raphael simulation and less than 2% delta to the real Si data at 28-nm node. Effects of the transition layer and the low-κ damage layer on capacitance and the impact of terminal capacitance on the coupling capacitance are discussed in detail.