DocumentCode :
654006
Title :
BaBaNoC: An asynchronous network-on-chip described in Balsa
Author :
Moreira, Matheus T. ; Magalhaes, Felipe ; Gibiluka, Matheus ; Hessel, Fabiano P. ; Calazans, Ney L. V.
Author_Institution :
Fac. of Comput. Sci., Pontifical Catholic Univ. of Rio Grande do Sul, Porto Alegre, Brazil
fYear :
2013
fDate :
3-4 Oct. 2013
Firstpage :
37
Lastpage :
43
Abstract :
The downscaling of silicon technology and the possibility of building MPSoCs, make intrachip communication a mainstream research topic. NoCs are an elegant solution to provide communication scalability and modularity. NoCs are already common in MPSoC design. Moreover, new technology challenges point to a growth in the use of non-synchronous NoCs. However, the design of asynchronous infrastructures with current EDA tools is challenging. That is due to the fact that most of these tools are oriented towards synchronous design. This work proposes and evaluates a fully asynchronous NoC router based on the Balsa language and framework. The design is validates through FPGA synthesis.
Keywords :
electronic design automation; field programmable gate arrays; network-on-chip; BaBaNoC; Balsa language; EDA tools; FPGA synthesis; MPSoC; asynchronous NoC router; asynchronous infrastructures; asynchronous network-on-chip; communication modularity; communication scalability; intrachip communication; silicon technology; Asynchronous circuits; Control systems; Delays; Ports (Computers); Protocols; Registers; Wires; Asynchronous circuits; network-on-chip; semi-custom;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Rapid System Prototyping (RSP), 2013 International Symposium on
Conference_Location :
Montreal, QC
Type :
conf
DOI :
10.1109/RSP.2013.6683956
Filename :
6683956
Link To Document :
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