A 3–5 GHz fully integrated CMOS UWB radar chip

Author

Seung Hwan Jung ; Jong Ok Ha ; Hyun Jin Yoo ; Chang Wook Cheong ; Yun Seong Eo ; Young-Hoon Chun ; Wan-Sik Kim

Author_Institution

Dept. of Electron. Eng., Kwangwoon Univ., Seoul, South Korea

fYear

2013

fDate

9-11 Oct. 2013

Firstpage

57

Lastpage

60

Abstract

A 3 - 5 GHz UWB radar chip for surveillance and reconnaissance applications is fabricated in 0.13um CMOS process. The UWB radar chip employs the equivalent time sampling and 4-channel time interleaved sampler architecture. The DC offset calibrator and BJT based circuit greatly reduce the DC offset issues. The analog signal processing part employs the proposed high speed track and hold (T/H) circuit. The direct loop back test shows the feasibility of the distance sensing with 3 cm resolution at the several meter distance. The chip size is 4 mm × 2.5 mm, and 81mA / 38mA (Rx/Tx) are consumed at 1.5 V supply.

Keywords

CMOS integrated circuits; bipolar transistors; sample and hold circuits; ultra wideband radar; 4-channel time interleaved sampler architecture; BJT based circuit; CMOS process; DC offset calibrator; direct loop back test; frequency 3 GHz to 5 GHz; fully integrated CMOS UWB radar chip; time sampling; track and hold circuit; Antenna measurements; CMOS integrated circuits; Calibration; Clocks; Radio frequency; Surveillance; Ultra wideband radar; CMOS Single Chip Radar; DC Offset Calibration; Digitally Synthesized Impulse Generator; UWB Radar;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar Conference (EuRAD), 2013 European

Conference_Location

Nuremberg

Type

conf

Filename

6689112