DocumentCode
657979
Title
A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications
Author
Ochoa-Ruiz, G. ; Touiza, M. ; Bourennane, E. ; Guessoum, Abderrezak ; Messaoudi, Kamel ; Hajjaji, Mohamed Ali
Author_Institution
LE2I Lab., Burgundy Univ., Dijon, France
fYear
2013
fDate
6-8 May 2013
Firstpage
271
Lastpage
276
Abstract
Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time overhead might proof prohibitive. In order to find the best compromise between these approaches, we make use of the OORBIT tool (Offline/Online Relocation of Bitstreams) which helps us to accelerate the PBR considerably. In this paper, we compare the developed tool to others in previous works, specifically in the context of many-core applications; we give a particular importance to the reduction in the relocation time, which must to increase the time overhead already incurred by using partial reconfiguration. In this paper, we show how the tool has been used in this context, and a comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation process more amenable.
Keywords
field programmable gate arrays; multiprocessing systems; reconfigurable architectures; OORBIT tool; PBR; Xilinx partial reconfiguration flow; large scalable system; many-core partially reconfigurable application; offline-online relocation of bitstreams; partial bitstream relocation; Discrete cosine transforms; Field programmable gate arrays; Hardware; Memory management; Registers; Resource management; Bitstream Relocation; Embedded Systems; FPGA; Partial Reconfiguration;
fLanguage
English
Publisher
ieee
Conference_Titel
Control, Decision and Information Technologies (CoDIT), 2013 International Conference on
Conference_Location
Hammamet
Print_ISBN
978-1-4673-5547-6
Type
conf
DOI
10.1109/CoDIT.2013.6689556
Filename
6689556
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