An FPGA implementation method of OFDM timing synchronization based on conjugated-symmetrical-structured training sequence

Timing synchronization is a critical technology in OFDM system, which affects the performance of the whole system greatly. An FPGA implementation method of OFDM timing synchronization is proposed in this paper, which uses only one conjugated-symmetrical -structured training sequence to achieve timing synchronization with high accuracy. To implement this timing synchronization method, we need three steps: fist, we generate an m sequence and noise sequence. Second, we construct the training sequence, and insert data symbols back of training sequence. At last, we find the position of the timing synchronization in OFDM receiver. All the sub-modules of synchronization circuit are described in Verilog-HDL and constructed by IP cores supplied by Xilinx. Finally, all these circuits are downloaded to virtex-6 FPGA development board ML-605 based on xc6Vlx240t-1ff1156 chip of Xilinx. Experiment results demonstrate that the timing position fall in the middle of the training sequence, which indicates correctness and validity of the scheme designed.