Design and error analysis of a OTA for high speed pipeline ADC

Author

Junfeng Yang ; Zheying Li

Author_Institution

Sch. of Electron. & Inf. Eng., Beijing Jiaotong Univ., Beijing, China

fYear

2013

fDate

29-31 Oct. 2013

Firstpage

679

Lastpage

683

Abstract

This work designs and simulates a high-speed low-power operational transconductance amplifier(OTA), which is used in a 100Msps, 8 bit pipeline ADC with 1.5 bit per stage. Primary objective of the design has been to analyze how the error of OTA (offset voltage and gain error) impact to the performance of ADC. The OTA use the circuit of fully differential telescopic cascode to get high gain and low power, it achieves 45dB voltage gain and the average offset voltage of this OTA is only 512.1uV.The ADC achieves 0.7LSB DNL and 0.9LSB INL with low power consumption from 1.8V supply.

Keywords

error analysis; operational amplifiers; OTA; error analysis; fully differential telescopic cascode; gain error; high speed pipeline ADC; high-speed low-power operational transconductance amplifier; offset voltage; Bandwidth; Educational institutions; Impedance; Integrated circuit modeling; MATLAB; Mathematical model; Pipelines; DNL; INL; OTA; SH; cascode; offset voltage; pipeline ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications (MAPE), 2013 IEEE 5th International Symposium on

Conference_Location

Chengdu

Print_ISBN

978-1-4673-6077-7

Type

conf

DOI

10.1109/MAPE.2013.6689932

Filename

6689932