Title :
Logisim to DEVS Translation
Author :
Van Tendeloo, Yentl ; Vangheluwe, Hans
Author_Institution :
Univ. of Antwerp, Antwerp, Belgium
fDate :
Oct. 30 2013-Nov. 1 2013
Abstract :
We propose a transformation from digital logic circuits modelled in the Logisim modelling language (and tool) to behaviourally equivalent models in the Discrete-EVent System specification (DEVS) formalism. This is achieved by mapping each Logisim component to a corresponding atomic DEVS model and by preserving the component coupling. The challenge in this work is the faithful preservation of all details of the Logisim semantics. The transformation is described and the translation of an example data path is given.
Keywords :
discrete event systems; logic circuits; simulation languages; DEVS translation; Logisim component mapping; Logisim modelling language; Logisim semantics; atomic DEVS model; component coupling; digital logic circuits; discrete-event system specification; Computational modeling; Hardware design languages; Integrated circuit modeling; Ports (Computers); Resistors; Semantics; Wires;
Conference_Titel :
Distributed Simulation and Real Time Applications (DS-RT), 2013 IEEE/ACM 17th International Symposium on
Conference_Location :
Delft
DOI :
10.1109/DS-RT.2013.10