Thermal Aware Don´t Care Filling to Reduce Peak Temperature and Thermal Variance during Testing

Temperature during testing has become an important issue to be considered with the continuous improvement of VLSI technology. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Also to bring uniformity in temperature distribution across the chip the thermal variance needs to be reduced. Temperature of a block depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation can be reduced by reducing transitions among test vectors. However, heat dissipation depends on thermal gradient. To reduce the peak temperature and thermal variance, the don´t care bits present in test vectors can be filled in such a way that the transitions of a block and also of its neighbors get reduced. In this paper we have proposed a don´t care filling technique which fills the don´t care bits in the test vectors in a way such that peak temperature and thermal variance as well as the peak power and average power get reduced. Experimental results of our proposed approach on ISCAS´89 benchmark circuits show an enriched reduction in peak temperature and thermal variance as well as in peak power and average power with nominal CPU time.