Title :
Scan Test Data Volume Reduction for SoC Designs in EDT Environment
Author :
Guoliang Li ; Jun Qian ; Yuan Zuo ; Rui Li ; Qinfu Yang
Author_Institution :
Adv. Micro Devices, Shanghai, China
Abstract :
This paper presents approaches to reduce scan test data volume for SoC designs in EDT environment. They target different factors impacting scan test data volume - scan channel count, pattern count and shift cycles. In the experiments on an industrial SoC design, up to 23% scan test data volume can be reduced.
Keywords :
integrated circuit design; integrated circuit testing; system-on-chip; EDT environment; SoC designs; embedded deterministic test; pattern count; scan channel count; scan test data volume reduction; shift cycle; system-on-chip; Algorithm design and analysis; Nickel; Ring generators; Schedules; Shift registers; System-on-chip; Embedded Deterministic Test (EDT); X-chain re-allocation; X-cluster; prediction based co-optimization; test data volume reduction; test schedule;
Conference_Titel :
Test Symposium (ATS), 2013 22nd Asian
Conference_Location :
Jiaosi Township
DOI :
10.1109/ATS.2013.27
