Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs

This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.