DocumentCode :
658569
Title :
Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations
Author :
Hsunwei Hsiung ; Da Cheng ; Bin Liu ; Govindan, Ramesh ; Gupta, Suneet K.
Author_Institution :
Electr. Eng. Dept., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2013
fDate :
18-21 Nov. 2013
Firstpage :
251
Lastpage :
258
Abstract :
As process variations grow with technology scaling, failure rates increase and are predicted to be so high as to render devices unusable for computing domain. In order to continue to benefit from scaling, three dimensions can be explored: increasing operational margins, testing, and the resilience of applications. The solutions in each dimension bring out different trade-offs in yield, failure rate, test cost, and performance. We use a ternary content-addressable memory (TCAM) as a case study to better understand these trade-offs. We develop two new delay tests for TCAMs, and a new method to estimate yield, failure rate, test cost, and performance of TCAM under process variations when various tests are used. Our results show that with little test overhead and negligible yield loss, our new tests can significantly decrease the failure rates of TCAMs shipped to customers.
Keywords :
content-addressable storage; integrated circuit testing; integrated circuit yield; TCAM; delay tests; failure rate; operational margins; process variations; ternary content-addressable memory; test cost; test overhead; yield loss; Arrays; Circuit faults; Delays; Logic gates; Random access memory; Testing; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2013 22nd Asian
Conference_Location :
Jiaosi Township
ISSN :
1081-7735
Type :
conf
DOI :
10.1109/ATS.2013.54
Filename :
6690650
Link To Document :
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