Title :
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
Author :
Kushida, K. ; Tachibana, F. ; Hirabayashi, O. ; Takeyama, Y. ; Shizuno, M. ; Kawasumi, A. ; Suzuki, A. ; Niki, Y. ; Sasaki, Seishi ; Yabe, Tatsuro ; Unekawa, Y.
Author_Institution :
Toshiba Corp. Semicond. & Storage Products Co., Kawasaki, Japan
Abstract :
This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; power consumption; BL power calculator; CMOS technology; RT; SRAM circuit techniques; active mode power reduction; bit line power calculator; cell supply voltage; control power; digitally controllable retention circuit; dual-power-supply SRAM; power consumption; room temperature; size 28 nm; standby mode power reduction; temperature 25 C; temperature 293 K to 298 K; Calculators; Leakage currents; Logic gates; Power demand; Random access memory; Temperature; Voltage control;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6690973
