DocumentCode :
658890
Title :
HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs
Author :
Jun Zhou ; Xin Liu ; Yat-Hei Lam ; Chao Wang ; Kah-Hyong Chang ; Jingjing Lan ; Minkyu Je
Author_Institution :
Inst. of Microelectron., A*STAR, Singapore, Singapore
fYear :
2013
fDate :
11-13 Nov. 2013
Firstpage :
129
Lastpage :
132
Abstract :
A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.
Keywords :
flip-flops; logic design; low-power electronics; Canary flip-flop; FFT processor; HEPP; PVT variations; Razor flip-flop; critical paths; fast dynamic variations; hold-time constraint; in-situ timing-error prediction; prevention technique; ultra-low-voltage digital designs; variation-tolerant ultra-low-voltage designs; Clocks; Delays; Flip-flops; Logic gates; Semiconductor device measurement; Tuning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
Type :
conf
DOI :
10.1109/ASSCC.2013.6690999
Filename :
6690999
Link To Document :
بازگشت