A 40nm, high bandwidth, VCO-based burst-mode receiver backend for EHF multi-carrier wireless

A receiver back-end in 40 nm CMOS for an EHF wireless multi-carrier applications is presented. The system is designed to reduce the bandwidth of a multi-tone I/Q decomposed wideband signal after which it is digitized and stored. The bandwidth reduction is applied by means of a reconfigurable sub-sampling operation. The integrated ADCs, performing the digitization, are a time-based dual 128-phase VCO topology implementation. On-chip data buffering of 96 kB is foreseen, capable of storing burst signals of a duration up to 8 μs. The IC is capable to process discrete spectra up to an RF bandwidth of 6 GHz originating from a downconverted 60 GHz signal. A measured effective resolution of 6 bits is realized thanks to the inherent first order noise shaping of the built-in ADC. The SFDR is measured at 40 dB. Power consumption for the complete I/Q core, sampling at 3 GHz, is measured to be 106 mW. The area of the 40 nm core is 0.162 mm².