Title :
A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS
Author :
Xubin Chen ; Yun Chen ; Yi Li ; Yuebin Huang ; Xiaoyang Zeng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.
Keywords :
3G mobile communication; CMOS integrated circuits; Long Term Evolution; WiMax; application specific integrated circuits; binary codes; interleaved codes; turbo codes; 3GPP-LTE systems; TSMC CMOS process; WiMAX systems; barrel shift networks; binary codes; bit rate 326.4 Mbit/s; bit rate 691 Mbit/s; distinct interleavers; duo-binary turbo codes; low-complexity address generator; power 193 mW; quad-bank memory partition; size 65 nm; unified parallel radix-16 turbo decoder ASIC; voltage 0.9 V; Application specific integrated circuits; Decoding; Measurement; Parallel processing; Throughput; Turbo codes; WiMAX; 4G mobile communication; ASIC implementation; LTE; Turbo decoder; WiMAX; interleaver; radix-16;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691006
