DocumentCode
658929
Title
A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS
Author
Guan-Ying Huang ; Soon-Jyh Chang ; Ying-Zu Lin ; Chun-Cheng Liu ; Chun-Po Huang
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2013
fDate
11-13 Nov. 2013
Firstpage
289
Lastpage
292
Abstract
This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; CMOS; FOM; SAR ADC; bypass window; control logic delay reduction; direct switching technique; power 0.82 mW; power consumption reduction; settling time reduction; size 40 nm; small unit capacitor cell; successive-approximation analog-to-digital converter; voltage 0.9 V; Capacitors; Frequency measurement; Latches; Power demand; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location
Singapore
Print_ISBN
978-1-4799-0277-4
Type
conf
DOI
10.1109/ASSCC.2013.6691039
Filename
6691039
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