Title :
Completely self-synchronous 1024-bit RSA crypt-engine in 40nm CMOS
Author :
Devlin, Benjamin ; Ikeda, Makoto ; Ueki, Hiroshi ; Fukushima, Kazuki
Author_Institution :
Xilinx, Tokyo, Japan
Abstract :
We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the performance of the self-synchronous, gate-level pipelined architectures. Both implementations employ identical data-paths and take 804k transistors, with only difference in controller, and two interleaved 1024b cryptographic operations take from 6.1ms to 3.1ms for HTL and 6.0ms for MPL, at nominal power supply of 1.1V.
Keywords :
pipeline processing; public key cryptography; CMOS; HTL power ladder; MPL; Montgomery power ladder; cryptographic operations; gate-level pipelined architectures; high-to-low power ladder; modular exponentiation algorithms; self-synchronous RSA crypt-engine; CMOS integrated circuits; Computer architecture; Cryptography; Logic gates; Pipeline processing; Solid state circuits; Timing; 1024bit; RSA; Self-Synchronous;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691044
