Title :
Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing
Author :
Alnajjar, Dawood ; Konoura, Hiroaki ; Mitsuyama, Yukio ; Shimada, Hiroki ; Kobayashi, Kaoru ; Kanbara, H. ; Ochi, Hiroshi ; Imagawa, T. ; Noda, Satoshi ; Wakabayashi, Kazutoshi ; Hashimoto, Mime ; Onoye, Takao ; Onodera, Hidetoshi
Author_Institution :
Dept. Inf. Syst. Eng., Osaka Univ., Osaka, Japan
Abstract :
This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment. Irradiation tests also show the correlation between the number of sensitive bits and the mean time to failure. Furthermore, the temporal error rate of an example application due to soft errors in the datapath were measured and demonstrated for reliability-aware mapping.
Keywords :
VLSI; consumer products; integrated circuit manufacture; integrated circuit reliability; radiation hardening (electronics); C-to-array application mapping; C-to-array mapping; consumer products; harsh radiation environment; irradiation tests; mixed-grained reconfigurable VLSI array architecture; proof-of-concept VLSI chip; radiation testing; reliability-aware mapping; reliability-configurable mixed-grained reconfigurable array; size 65 nm; soft errors; very large scale integration; Arrays; Radiation effects; Registers; Reliability; Table lookup; Tunneling magnetoresistance; behavioral synthesis; heterogeneous array; radiation test; reconfigurable architecture; soft error;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691045