A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS

This paper proposes two techniques for improving the linearity and power efficiency of switched-capacitor (SC) circuits. The first is a high-speed switched-current-assisting (SCA) path that helps the main (folded-cascode) OTA to deliver most of the desired charge to the integration capacitor, leaving the final error correction to be completed by the main OTA. The second is a pre-charging (PC) path that assists the main OTA to speed up the charging of the load capacitor. Both SCA and PC paths share one auxiliary (differential-pair) OTA that features a high speed-to-power efficiency. The prototype is a bandwidth-scalable 5^th-order Butterworth SC lowpass filter (LPF) for software-defined radios. Fabricated in 65-nm CMOS, the LPF exhibits a decade-wide tunable bandwidth (1.5 to 15 MHz) solely defined by the clock, leading to a compact die size (0.127 mm²). Under the same power (5.6 mW) and bandwidth (10 MHz) targets, the IIP3 reaches +23.5 dBm (+15.3 dBm) and the cutoff accuracy is 97% (82%) with (without) the SCA + PC paths. The achieved Figure-of-Merit (0.014 fJ) compares favorably with the state-of-the-art.