Automatic test pattern generation for delay defects using timed characteristic functions

Testing integrated circuits under delay defects becomes an essential quality control step in nanometer fabrication technologies, which encounter inevitable process variations. Prior methods on automatic test pattern generation (ATPG) for delay defects, however, are either overly simplified (e.g., timing unaware) or computationally too expensive. This paper proposes a viable ATPG method based on a satisfiability (SAT) formulation using timed characteristic functions (TCFs), which gained notable scalability enhancement very recently. The approach provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over prior SAT-based timing-aware ATPG methods. Moreover, our method provides a nice complement to commercial tools in enhancing test quality.