Improving platform energy-chip area trade-off in near-threshold computing environment

Recent studies on near-threshold computing (NTC) investigated an optimum supply voltage which yields minimum energy per operation (E_min), and proposed various optimization techniques at the device, circuit, and architecture levels to further minimize E_mn. However, most of these studies often overlooked the significance of (i) energy consumption of off-chip memory accesses; (ii) energy loss of voltage regulators (VRs); and (iii) the cost of chip area in NTC environment. In this paper, we first demonstrate the increasing significance of (i) and (ii) in NTC environment with a comprehensive set of device, circuit, and architectural-level models. Second, we explore technology optimization to improve the trade-off between platform energy and chip area considering (iii) in NTC environment. The experimental results show that our optimized technology achieves 4% to 21% energy reduction for various chip area constraints, achieving significant improvement in trade-off between platform energy and chip area for a wide range of parallel benchmarks.