Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

In this paper, we present a transient modeling of electromigration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs. In particular, we model atomic depletion and accumulation, effective resistance degradation, and full chip-scale PDN lifetime degradation due to EM. Our major focuses are on: (1) time-dependent multi-physics EM modeling approach to model TSVs and connecting wires under the influence of coupled physical phenomenon including electric field, temperature, and stress; (2) time-dependent EM-aware power integrity analysis methodology, which is integrated with the TSV modeling approach to predict long-term IR-drop degradation in full-chip 3D power delivery networks. Our studies show that voids and hillocks grow at various TSV-to-wire interfaces and degrade the effective resistance of TSVs significantly. In addition, our full-chip PDN lifetime analysis shows significant increase in maximum IR drop during lifetime due to EM effects.