DocumentCode
659040
Title
Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems
Author
Beletsky, Platon ; Chunkuen Ho ; Bershteyn, Mike ; Salitrennik, Viktor ; Birguer, Alexandre
Author_Institution
Cadence Design Syst., San Jose, CA, USA
fYear
2013
fDate
18-21 Nov. 2013
Firstpage
473
Lastpage
477
Abstract
In this paper, we describe special techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems. We will examine performance of such systems and the methods for improving it by reducing the redundant evaluations, memory mapping optimizations, partitioning and scheduling.
Keywords
logic design; multiprocessing systems; performance evaluation; processor scheduling; redundancy; large scale logic design models; massively parallel fine-grained multiprocessor systems; memory mapping optimization reduction; partitioning reduction; redundant evaluation reduction; scheduling reduction; Arrays; Delays; Emulation; Logic gates; Memory management; Multiprocessing systems; Ports (Computers); emulation; simulation; verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2013.6691159
Filename
6691159
Link To Document