DocumentCode :
659071
Title :
Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion
Author :
Kahng, Andrew ; Ilgweon Kang ; Nath, Siddhartha
Author_Institution :
ECE Depts., UC San Diego, La Jolla, CA, USA
fYear :
2013
fDate :
18-21 Nov. 2013
Firstpage :
705
Lastpage :
712
Abstract :
Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss of test coverage, ECO flip-flops must be added into existing scan chains with minimal increase to test time and minimal impact on existing routing and timing slack. We address a new Incremental Multiple-Scan Chain Ordering problem formulation to automate the tedious and time-consuming process of scan stitching for large functional ECOs. We present a heuristic with clustering, incremental clustering and ordering steps to minimize the maximum chain length (test time), routing congestion, and disturbance to existing scan chains. Test times for our incremental scan chain solutions are reduced by 5.3%, and incremental wirelength costs are reduced by 45.71%, compared to manually-solved industrial testcases.
Keywords :
boundary scan testing; flip-flops; network routing; ECO flip-flop insertion; ECO logic; SOC implementation flow; design revisions; front-end designers; incremental multiple-scan chain ordering; maximum chain length; routing congestion; routing slack; scan stitching; scheduled tapeout dates; test coverage; test time; timing slack; Iron; Optimization; Routing; Timing; Upper bound; Vectors; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2013.6691192
Filename :
6691192
Link To Document :
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