Title :
Design of low power comparator circuit based on reversible logic technology
Author :
Shukla, H.P. ; Rao, A.G. ; Mall, Prerak
Author_Institution :
Gorakhpur Centre, NIELIT, Gorakhpur, India
Abstract :
In this paper, a new 4×4 reversible logic gate named “PR” (Pallavi-Raman) gate has been proposed for application in low power comparator design. Based on PR gate, a four bi t reversible comparator circuit has been designed and was found that the proposed design is better in terms of garbage outputs, no. of reversible gates used, quantum cost and no. of constants inputs than previous designs. PR gate can also be used to perform various operations like, subtraction, copier AND, NAND, XOR, XNOR and NOT gate, thus working as a Reversible Logic Universal Gate.
Keywords :
comparators (circuits); logic design; logic gates; low-power electronics; 4×4 reversible logic gate; NAND gate; NOT gate; Pallavi-Raman gate; XNOR gate; XOR gate; copier AND gate; low power comparator circuit; quantum cost; reversible comparator circuit; reversible logic universal gate; subtraction; Bismuth; Delays; Heating; Logic circuits; Logic gates; Optimization; Power demand; Comparator; Constant Input; Garbage Output; Quantum Cost; Reversible Logic Technology (RLT);
Conference_Titel :
Emerging Trends and Applications in Computer Science (ICETACS), 2013 1st International Conference on
Conference_Location :
Shillong
Print_ISBN :
978-1-4673-5249-9
DOI :
10.1109/ICETACS.2013.6691385
