Double-gate junctionless transistor for low power digital applications

In this paper, the performance of a short channel symmetric double-gate junctionless transistor (DGJLT) is reported at lower drain voltage aiming low power digital applications. The performance parameters namely drain current (I_D), threshold voltage (V_T), subthreshold slope (SS), drain induced barrier lowering (DIBL), and ON-state to OFFstate current ratio (I_ON/I_OFF) for an n-channel DGJLT are systematically investigated with the help of extensive device simulations. The device characteristics are compared with inversion mode counterpart i.e., double-gate metal-oxide-semiconductor (DGMOS) of similar dimension. DGJLT is found to have significantly overall better performance compared to inversion mode DGMOS transistor at lower drain voltage.