Hybrid ARQ Performance Improvement with Decoder Input Refining

In this paper, some implementation issues associated with Hybrid ARQ processing are investigated. It is first shown that bit level and symbol level Chase combining are identical in performance for QPSK. However, the symbol level combining results in better performance in case of higher order modulations, such as 16QAM and 64QAM. Then, in order to further improve symbol level chase combining performance, a new method of bit level log-likelihood ratio (LLR) refining based on iterative channel decoder intermediate results is presented. Simulation results indicate significant performance gain can be achieved with the decoder input refining scheme.