A hardware-efficient variable-length FFT processor for low-power applications

The fast Fourier transformation (FFT) is a key operation in digital signal processing (DSP) systems and has been studied intensively to improve the performance. Nowadays, embedded DSP systems require low energy consumption to prolong the life cycle, which raises stringent power limitation for FFT processing. Meanwhile, sufficient signal-to-quantization-noise ratio (SQNR) is a basic requirement in these systems. In this paper, a modified data scaling scheme as well as trounding method is employed to improve the SQNR performance. Therefore word-length can be reduced and energy is saved accordingly. Memory-based architecture is chosen to support variable-length FFT processing. Also, constant multiplier array is introduced in the datapath to reduce the power dissipation with a slight increase of area. The proposed processor can perform 64-8192-point FFT processing. The core area is 2.29 mm² and the power consumption is 67.9 mW at 100MHz. Besides, the SQNR of 55.4 dB and 33.3 dB are achieved for 64-point and 8192-point FFT respectively.