DocumentCode :
661567
Title :
Suppression of threshold voltage shift for normally-Off GaN MIS-HEMT without post deposition annealing
Author :
Kanamura, M. ; Ohki, T. ; Ozaki, S. ; Nishimori, M. ; Tomabechi, S. ; Kotani, J. ; Miyajima, T. ; Nakamura, N. ; Okamoto, N. ; Kikkawa, T. ; Watanabe, K.
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
fYear :
2013
fDate :
26-30 May 2013
Firstpage :
411
Lastpage :
414
Abstract :
In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al2O3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al2O3 deposited at high temperature achieve high quality interface and bulk without post deposition annealing (PDA), preventing the degradation of electrodes and crystallization of insulator film. The fabricated device shows small C-V and I-V hysteresis, with a breakdown voltage of greater than 600 V.
Keywords :
III-V semiconductors; alumina; crystallisation; dielectric thin films; gallium compounds; high electron mobility transistors; wide band gap semiconductors; Al2O3; C-V hysteresis; GaN; I-V hysteresis; dielectric deposition conditions; electrode degradation; high quality interface; high-temperature deposition; insulator film crystallization; normally-off MIS-HEMT; positive gate voltage operation; threshold voltage shift suppression; Aluminum gallium nitride; Aluminum oxide; Capacitance-voltage characteristics; Gallium nitride; Hysteresis; Insulators; Logic gates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
ISSN :
1943-653X
Print_ISBN :
978-1-4673-5134-8
Type :
conf
DOI :
10.1109/ISPSD.2013.6694432
Filename :
6694432
Link To Document :
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