Development of a highly efficient and linear differential CMOS power amplifier with harmonic control

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with a second harmonic circuit at the common-gate (CG) stage. The proposed single stage PA including the harmonic control circuit is fabricated using 0.18-μm RF CMOS technology with a printed board circuit based output transformer. The impact on the nonlinearity of the common-gate stage is analyzed. The CMOS PA module achieves a power added efficiency (PAE) of 38.7%, an error vector magnitude (EVM) of 5.4%, and the adjacent channel leakage ratio (ACLR) of -30.4 dBc at the average output power of 27.8 dBm and the frequency of 1.85 GHz for the 10-MHz bandwidth (BW) 16-QAM 7.5-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal.