DocumentCode :
664353
Title :
A 60 GHz CMOS power amplifier with modified pre-distortion linearizer
Author :
Yu-Chung Hsu ; Kun-Yao Kao ; Jui-Chih Kao ; Tzung-Chuen Tsai ; Kun-You Lin
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2013
fDate :
2-7 June 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper proposes a new pre-distortion linearizer for CMOS power amplifier (PA) to improve the performance of the output 1-dB compression power and power added efficiency at 1-dB compression power. By adopting the proposed pre-distortion linearizer, a 60 GHz cascode PA with 13.7-dBm 1-dB compression power (P1dB) and 14.3% power added efficiency (PAE) at P1dB is demonstrated. The chip size is 0.55 × 0.45 mm2 including all testing pads.
Keywords :
CMOS analogue integrated circuits; distortion; linearisation techniques; power amplifiers; CMOS power amplifier; PAE; cascode PA; compression power; frequency 60 GHz; power added efficiency; CMOS integrated circuits; CMOS process; Delay lines; Gain; Power amplifiers; Power generation; 60 GHz; CMOS; Power amplifiers; pre-distortion linearizer;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Symposium Digest (IMS), 2013 IEEE MTT-S International
Conference_Location :
Seattle, WA
ISSN :
0149-645X
Print_ISBN :
978-1-4673-6177-4
Type :
conf
DOI :
10.1109/MWSYM.2013.6697359
Filename :
6697359
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=664353
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