A fully-integrated high power wideband power amplifier in 0.25 μm CMOS SOS technology

A fully-integrated wideband power amplifier (PA) is implemented in 0.25 μm CMOS silicon-on-sapphire (SOS) technology. The PA is designed with 4 stacked dynamically biased Cascode cells to increase the overall output voltage swing as well as the output impedance. The fully-insulating substrate in the SOS process significantly suppresses the effect of parasitic capacitance and hence minimizes the amplitude and phase differences among drain-source voltage waveforms across each transistor. The PA measures a saturated output power (P_SAT) of 34.4 dBm (2.75 W) at 1.4 GHz with a peak PAE and corresponding DE of 38% and 48%, respectively, when biased under a 16 V supply. The measured output power is above 33 dBm (2 W) from 1 to 1.8 GHz. The linearity of the PA is measured with both uplink WCDMA and 10 MHz QPSK LTE signals at 1.4 GHz. The measured output power at ACLR of -33 dBc is 29.2 dBm for the WCDMA signal and 26.3 dBm for the LTE signal. The stacked PA occupies a compact chip area of 2.2 mm².