An 800 MSPS quadrature DDFS and integrated nonlinear DAC-filter with <15 ns instantaneous frequency hopping time

An 800 MSPS quadrature Direct Digital Frequency Synthesizer (DDFS) with an integrated 13-bit nonlinear DAC and a 200 MHz spur-rejection filter is presented. The system consists of a 10 ns latency ROM-less DDFS and a sine-weighted, current-steering DAC with a layout technique conducive to the DDFS algorithm. A 200 MHz active OTA-RC spur-rejection filter follows the DDFS-DAC giving > 60 dB rejection at 600 MHz with an IIP3 of 25 dBm. The system achieves an SFDR ≈ 33 dB and a total instantaneous hopping time of 15 ns. The system is designed and fabricated in a 0.13 μm CMOS technology, has a total chip area of 2.54 mm × 2.96 mm, and consumes 420 mW of power.