A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

This paper presents a novel on-chip interconnect system for multi-core chips using transmission lines as shared media. It supports both point-to-point and broadcasting communications. Compared to network-on-chip approaches, it offers significant advantages in circuit complexity, energy efficiency and link latency. To demonstrate the scheme, a chip prototype with two 20-mm long transmission lines running in parallel and multiple transmitters/receivers (including 2:1 serializer/1:2 deserializer) was implemented in a 130-nm SiGe BiCMOS technology. The prototype can achieve a date rate of 25.4 Gb/s with an energy efficiency of 1.67 pJ/b in the measurement.