A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

Author

Jianyun Hu ; Jie Xu ; Huang, Meng ; Hui Wu

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA

fYear

2013

fDate

2-7 June 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a novel on-chip interconnect system for multi-core chips using transmission lines as shared media. It supports both point-to-point and broadcasting communications. Compared to network-on-chip approaches, it offers significant advantages in circuit complexity, energy efficiency and link latency. To demonstrate the scheme, a chip prototype with two 20-mm long transmission lines running in parallel and multiple transmitters/receivers (including 2:1 serializer/1:2 deserializer) was implemented in a 130-nm SiGe BiCMOS technology. The prototype can achieve a date rate of 25.4 Gb/s with an energy efficiency of 1.67 pJ/b in the measurement.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; circuit complexity; microprocessor chips; multiprocessing systems; transceivers; BiCMOS technology; SiGe; bit rate 25 Gbit/s; broadcasting communication; circuit complexity; energy efficiency; link latency; multicore chips; network on chip approach; on-chip communication; on-chip interconnect system; point to point communication; size 130 nm; size 20 mm; transmission line; Integrated circuit interconnections; Power transmission lines; Prototypes; Receivers; System-on-chip; Transmission line measurements; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest (IMS), 2013 IEEE MTT-S International

Conference_Location

Seattle, WA

ISSN

0149-645X

Print_ISBN

978-1-4673-6177-4

Type

conf

DOI

10.1109/MWSYM.2013.6697762

Filename

6697762