A low-power Adaboost-based object detection processor using Haar-like features

Author

Kimura, Mizue ; Matai, Janarbek ; Jacobsen, Matthew ; Kastner, Ryan

Author_Institution

Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA

fYear

2013

fDate

9-11 Sept. 2013

Firstpage

203

Lastpage

206

Abstract

This paper presents an architecture of a low-power real-time object detection processor using Adaboost with Haar-Like features. We employ a register array based architecture, and introduce two architectural-level power optimization techniques; signal gating domain for integral image extraction, and low-power integral image update. The power efficiency of our proposed architecture including nine classifiers is estimated to be 0.64mW/fps when handling VGA(640 × 480) 70fps video.

Keywords

Haar transforms; computer graphics; energy conservation; feature extraction; image classification; learning (artificial intelligence); low-power electronics; object detection; optimisation; parallel architectures; Haar-like features; VGA handling; architectural level power optimization technique; image classifier; integral image extraction; low power AdaBoost-based object detection processor; low power integral image update; power efficiency estimation; register array based architecture; signal gating domain; Arrays; Feature extraction; Multiplexing; Object detection; Power demand; Registers; Haar-Like features; Object detection; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics ?? Berlin (ICCE-Berlin), 2013. ICCEBerlin 2013. IEEE Third International Conference on

Conference_Location

Berlin

Print_ISBN

978-1-4799-1411-1

Type

conf

DOI

10.1109/ICCE-Berlin.2013.6697982

Filename

6697982