Design of instruction decode logic for dual-issue superscalar processor based on LEON2

An instruction decode logic available for dual-issue pipeline processor is presented in this paper. The structure is based on the LEON2 scalar processor since it is a multifunctional processor widely used in many application scenarios. Focusing on the decode part, mainly three problems are solved. A comparator that can help to get the right nPC (nest program counter) is introduced for instruction dispatching. Dependences between two instructions in parallel are settled by the added Branch detector, and operands hand over to each other between the two pipelines are implemented by brought in forwarding roads. Structure block diagrams of the dual-issue pipeline and the new function units added are given. Run testing program Dhrystone on the two different structures, results indicate that the performance of the dual-issue structure is improved by 30.18% comparing to the single-issue structure.