Partial page buffering for consumer devices with flash storage

As the capacity of the NAND flash memory increases rapidly, flash storage device needs to maintain larger amount of storage metadata (e.g., mapping information), which necessitates larger amount of hardware resources such as DRAM. Therefore, for storage manufacturers, it is needed to develop a novel scheme that minimizes the amount of storage metadata while preserving the storage performance. One of the effective approaches to cope with the increased storage capacity is enlarging the mapping unit to decrease the amount of mapping information. However, larger mapping unit can greatly increase the number of internal Read-Modify-Write operations which is very costly. In this paper, we propose the `Partial Page Buffering´ scheme, in which only partial page write requests are buffered, to reduce the Read-Modify-Write operations in storage devices. The proposed scheme enables us to increase the mapping unit size while preserving the storage performance.