A power efficient 6-bit TIQ ADC design for portable applications

Analog to digital converter (ADC) is an integral part of the system on chip(SoC)product because it plugs the gap between the analog physical world and digital logical world. Low power and low voltage requirements are becoming increasingly important issues as the MOSFET channel length shrinks below 0.25 submicron in the digital domain. In addition, SoC trends compel ADCs to be integrated on a chip with other digital circuits. Hence a power efficient ADC became an important module for long lifespan of battery for the portable appliances. The high speed and low power ADC design is achieved by using TIQ(threshold inverting quantization) comparator instead of traditional high gain differential comparator, and the decoder is designed using multiplexer instead of traditional ROM decoder. Multiplexer based decoder is modified in this paper to get lesser fan-out in critical path which reduces delay of encoder and more symmetrical and more regular structure to reduce area of circuit. The static error DNL/INL and dynamic parameter SFDR and SNDR are analyzed for the designed model. Simulated result with UMC180 nm CMOS technology in CADENCE VIRTUSO platform shows that the proposed model achieves high speed, low power consumption, low voltage operation compared to other conventional ADCs.