DocumentCode :
664929
Title :
A constraint-based watermarking technique using Schmitt Trigger insertion at logic synthesis level
Author :
Thai-Bao Huynh ; Trong-Thuc Hoang ; Trong-Tu Bui
Author_Institution :
Digital Signal Process. & Embedded Syst. Lab. (DESLab), Univ. of Sci., Ho Chi Minh City, Vietnam
fYear :
2013
fDate :
16-18 Oct. 2013
Firstpage :
115
Lastpage :
120
Abstract :
Although the advancement in Intellectual Property (IP) design increases rapidly, it is easy to copy and resell IP cores without noticing its owners. As a consequence, IP Protection (IPP) using watermarking has emerged as the state-of-the-art technique and raises numerous interests from many Integrated Circuit (IC) designers. In this paper, we propose a constraints-based watermarking technique to embed a signature in the design in order to prove the copyright of the IP makers. Our method carefully selects a list of candidate nets for embedding watermark. Then, a bit `1´ in the stream of watermarking bits is defined by adding a pair of improved Schmitt Trigger circuits to the corresponding net. Besides using the ASCII string of the signature, two hash functions, i.e. MD5 and BASE64, are utilized to create a unique stream of watermarked bits. The experimental results show that our proposed method has the ability to preserve the original functionality, performance of the design, and low overhead of the watermarked circuit. Specifically, when the proposed technique is applied into the 720-cell simple CPU IP core, there are 0% and 12% increase in delay and area overhead, respectively. Furthermore, if it is applied into practical circuits with millions cells, the area overhead will be approximately to 0%.
Keywords :
cryptography; industrial property; integrated circuit design; logic design; trigger circuits; watermarking; ASCII string; BASE64 hash function; CPU IP core; MD5 hash function; Schmitt trigger insertion; constraint based watermarking technique; constraints based watermarking technique; embedding watermark; integrated circuit design; intellectual property design; logic synthesis level; Delays; IP networks; Integrated circuit modeling; Layout; Trigger circuits; Watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Technologies for Communications (ATC), 2013 International Conference on
Conference_Location :
Ho Chi Minh City
ISSN :
2162-1020
Print_ISBN :
978-1-4799-1086-1
Type :
conf
DOI :
10.1109/ATC.2013.6698089
Filename :
6698089
Link To Document :
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