DocumentCode :
664980
Title :
Heterogeneous hardware accelerator architecture for streaming image processing
Author :
Cuong Pham-Quoc ; Al-Ars, Zaid ; Bertels, Koen
fYear :
2013
fDate :
16-18 Oct. 2013
Firstpage :
374
Lastpage :
379
Abstract :
This paper proposes a heterogeneous hardware accelerator architecture to support streaming image processing. Each image in a data-set is pre-processed on a host processor and sent to hardware kernels. The host processor and the hardware kernels process a stream of images in parallel. The Convey hybrid computing system is used to develop our proposed architecture. We use the Canny edge detection algorithm as our case study. The data-set used for our experiment contains 7200 images. Experimental results show that the system with the proposed architecture achieved a speed-up of the kernels by 2.13× and of the whole application by 2.40× with respect to a software implementation running on the host processor. Moreover, our proposed system achieves 55% energy reduction compared to a hardware accelerator system without streaming support.
Keywords :
edge detection; image processing; media streaming; Canny edge detection algorithm; Convey hybrid computing system; hardware kernels; heterogeneous hardware accelerator architecture; host processor; software implementation; streaming image processing; Clocks; Computer architecture; Hardware; Image edge detection; Kernel; Streaming media;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Technologies for Communications (ATC), 2013 International Conference on
Conference_Location :
Ho Chi Minh City
ISSN :
2162-1020
Print_ISBN :
978-1-4799-1086-1
Type :
conf
DOI :
10.1109/ATC.2013.6698140
Filename :
6698140
Link To Document :
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