Title :
A novel 10bit 90MS/s 2b/cycle SAR ADC
Author :
Hualing Wu ; Qiao Meng ; Hao Zhi
Author_Institution :
Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China
Abstract :
A 10-bit 90MS/s Successive Approximation Register (SAR) analog-to-digital converter (ADC) is realized in TSMC 0.18μm CMOS process. With 2b/cycle technique and new proposed asynchronous control logic, the proposed SAR ADC achieves rapid conversion rate, low power, leading to SNDR of 55.3 and SFDR of 64.7 at 90MS/s with 43M input. The active area with the digital calibration is 0.6×0.8mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; flip-flops; ADC; CMOS; SAR; analog-to-digital converter; asynchronous control logic; digital calibration; size 0.18 mum; successive approximation register; word length 10 bit; Approximation methods; CMOS integrated circuits; Calibration; Capacitors; Registers; Switches; Timing; 2b/cycle ADC; Successive Approximation Register (SAR); analog to digital converter (ADC);
Conference_Titel :
Advanced Technologies for Communications (ATC), 2013 International Conference on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-1-4799-1086-1
DOI :
10.1109/ATC.2013.6698170
