A Digitally Assisted Amplitude Calibration Technique for Phase-Locked Loop Systems

A digitally assisted amplitude calibration technique suitable for wideband phase-locked loops (PLLs) is presented in this paper. By operating the voltage-controlled oscillator in the current-limited region with a tunable bias scheme, an amplitude control mechanism is incorporated in the PLL system for performance optimization. Due to the use of a sequential search algorithm for amplitude calibration, the risk of locking failure is alleviated while maintaining a reasonable settling time. Using a 65-nm CMOS process, a 5-GHz wideband PLL with the proposed amplitude calibration is fabricated for a demonstration. Within the phase-locked frequency range from 4.6 to 6 GHz, the experimental results indicate output power variations of less than 2 dB as the calibration function is activated. Operating at an output frequency of 5 GHz, the measured output power and phase noise at 1-MHz offset frequency are -3.63 dBm and -105.8 dBc/Hz, respectively.