Hardware design of spatial mapper for 1.73Gbps multi-user MIMO system of IEEE802.11ac

This paper presents a spatial mapper hardware design using model based RTL provided by Synphony HLS. It is a part of a transmitter system based on IEEE 802.11ac. The speed target is 160MHz in the FPGA Altera Stratix IV EP4SE820H35C3. For spatial mapper, this speed can be achieved by two stages pipelining. The first pipeline puts inside of the complex multiplier, while the other is after the complex multiplier processing. The compilation result shows that the spatial mapper design can reach up to 203.7MHz and requires 1658 combinational circuits, 2113 ALMs, 3216 registers.