Silicon embedded line integration for high end passive silicon interposer

As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging. Especially for high end applications where several processor needs to communicate together, this approach could enhance the performances of whole systems. However there are many requirements for this type of packaging and some of the most challenging are the thin wafer processing and the bow management which are linked with integration schemes. This study proposes to compare three different types of integration for the front side first redistribution level at the top of 10μm diameter 80μm deep TSV in the framework of silicon interposer integration. The first integration is a simple damascene process. The second integration is a semi-additive process which offers possibility of thick copper lines but is more complex to stack with further rerouting levels. The last integration is an original integration developed in Léti called silicon embedded line (SEL) integration: the first line pattern is etched, like the TSV, inside the silicon.