A unique FPGA for the implementation of neural strategies for identifying harmonic distortions

In this paper, three optimized neural harmonics extraction methods are presented and compared in terms of simulation results, FPGA implementation and practical considerations. Those distortion identification schemes are used in nonlinear loads compensation with Active Power Filters (APF). This optimization is performed in order reduce the number of hardware resources required for digital implementations. The given approaches tend to use only one Adaline and remain powerful even under unbalanced conditions of voltage. In this way, the implementation of all the functionalities of the active filter control has been realized by means of a unique FPGA chip. Moreover, even the most consuming method (i.e., the ITM) uses less than 52% of hardware resources. Even though the mp-q technique (based on the instantaneous reactive power theory) is not the fastest in terms of hardware response time, it stills appear the most powerful for its filtering aptitudes with an experimental source-side current THD of 3.3% after compensation.